1. Field of the Invention
The present invention relates to design of circuitry for asynchronous inter-chip communications. More specifically, the present invention relates to a method and apparatus for controlling and matching speeds of operation between different asynchronous chips.
2. Related Art
As computer system clock speeds become progressively faster, it is becoming increasingly harder to synchronize the actions of computer system components with reference to a centralized system clock. To deal with this problem, computer system designers are beginning to investigate the use of asynchronous circuits that operate in a self-timed manner, without having to adhere to the constraints imposed by a centralized system clock.
While asynchronous operation circumvents limitations imposed by a centralized system clock, it also introduces new problems, especially with regards to inter-chip communications. In particular, when two communicating asynchronous chips operate at different speeds, a slower receiving chip can encounter an input-buffer overflow if a faster transmitting chip transmits a large amount of data at a higher speed.
A number of factors contribute to differences in chip speeds. First, different fabrication technologies lead to different chip speeds. For example, chips fabricated using 350 nm CMOS technology are likely to operate at a different speed than chips fabricated using 130 nm CMOS technology. Furthermore, because of process variations during fabrication and environmental factors, such as temperature and power supply variations, even two chips fabricated using the same technology can operate at different speeds.
To maintain error-free communications between asynchronous chips while achieving good performance, it is desirable to operate all the chips at the highest possible speed without overflowing the input buffer of any given chip. This usually requires all of the asynchronous chips to operate at the maximum speed of the slowest chip.
Hence, what is needed is a method and apparatus for controlling and matching the speeds of operation between asynchronous chips.